Taking AIMS at Digital Design by Axel Jantsch

Author:Axel Jantsch
Language: eng
Format: epub
ISBN: 9783031356056
Publisher: Springer Nature Switzerland

6.1 Counter Design in AIMS

A counter is a universally useful component present in virtually all hardware designs. Hence, it is useful to know the options and variants available. Broadly speaking, we can go for a synchronous or an asynchronous counter.

6.1.1 Synchronous Counter

Every counter consists of a set of FlipFlops (FFs), the register, where the counter value is stored, and combinational logic, which determines how the counter value is updated. In a synchronous counter, the register is controlled by a clock signal, and a counter value update is triggered by a clock edge.

Figure 6.1 shows a 4-bit counter which increments its value at every clock edge when the enable signal is 1. The top-most FF holds the least significant bit and toggles at every clock edge. The other FFs below toggle only at the clock edge if all FFs above are 1. Thus the counter register evolves through the values .

Fig. 6.1 A 4-bit synchronous counter. The FF on the top holds the least significant bit and the one at the bottom the most significant bit

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